Should All Pakistani Students Studying in Universities Complete A Year of Community Service

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                  Our universities are like our mothers. They take our grooming factor to heights. They build up our communication skills. They tell us how to present things in front of others. They make up our body languages and most of all they take our confidence to infinity by removing all hesitations. Our universities especially public sectors provide us international level degree at very low and affordable cost which help us avail great opportunities. They polish our skills and make us able to do something creative and extraordinary. Universities nourish and groom us for years and surely, they have right over any one year of our life as well. We get services and nourishment from our universities and government.                We are quite lucky we because we got such things in our lives but there are millions of children on roads in Pakistan. Those students aren't lucky enough to get care from our society or government. They don't get proper nourishment. They don'
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Verilog HDL using Data Flow

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Verilog codes using Data Flow



Create 4x1 Mux using Data Flow

Module

module Four_by_One(
    output out,
    input i0,
    input i1,
    input i2,
    input i3,
    input s0,
    input s1
    );
    
 assign out = (s1)?(s0?i3:i2):(s0?i1:i0);
endmodule

Test Bench

module Test_Four_by_One;

reg I0,I1,I2,I3;
reg S1,S0;
wire OUT;
Four_by_One mymux(OUT,I0,I1,I2,I3,S1,S0);
initial
begin
I0=1;I1=0;I2=0;I3=1;
#10 
S1=0;S0=0;
#10 
S1=0;S0=1;
#10 
S1=1;S0=0;
#10 
S1=1;S0=1;
end
endmodule

Create 16x1 using Data Flow using 4x1

Module

module Sixteen_by_One(
    output out,
    input i0,
    input i1,
    input i2,
    input i3,
    input i4,
    input i5,
    input i6,
    input i7,
    input i8,
    input i9,
    input i10,
    input i11,
    input i12,
    input i13,
    input i14,
    input i15,
    input s0,
    input s1
    );
    wire out1,out2,out3,ou4;
    assign out1=(s1)?(s0?i3:i2):(s0?i1:i0);
    assign out2=(s1)?(s0?i7:i6):(s0?i5:i4);
    assign out3=(s1)?(s0?i11:i10):(s0?i9:i8);
    assign out4=(s1)?(s0?i5:i14):(s0?i13:i12);
    
    assign out=(s1)?(s0?out4:out3):(s0?out2:out1);
endmodule

Test Bench

module Test_Sixteen_by_One;

reg I0,I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15;
reg S1,S0;
wire OUT;

Sixteen_by_One mymux(OUT,I0,I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15,S1,S0);
initial
begin
I0=1;I1=0;I2=1;I3=0;
I4=0;I5=1;I6=0;I7=1;
I8=1;I9=0;I10=0;I11=1;
I12=0;I13=1;I14=1;I15=0;
#10
S1=0;S0=0;
#10
S1=0;S0=1;
#10
S1=1;S0=0;
#10
S1=1;S0=1;
end
endmodule

Flip Flop using Data Flow

Module

module FlipFlop(
    output q,
    output qbar,
    input clear,
    input clk,
    input d
    );

wire cbar, sbar, s, r, rbar, clk1;
//NOT OF INPUTS
assign cbar= ~clear;
assign clk1= ~clk;
// GATES 
assign sbar=~(rbar & s);
assign s= ~(sbar & cbar & clk1);
assign r=~(s & clk1 & rbar);
assign rbar=~(r & cbar & d);
//OUTPUTS
assign q=~(s & qbar);
assign qbar=~(q & cbar & r);  
endmodule

Test Bench

module Test_FlipFlop();
wire q,qbar;
reg clear,clk,d;

FlipFlop myflip(q,qbar,clear,clk,d);
initial
begin
clk=1;
clear=1;d=0;
#20
clear=0;d=1;
#20
clear=1;d=1;
#20
clear=0;d=0;
end
always
#20 clk=~clk;
endmodule

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