Should All Pakistani Students Studying in Universities Complete A Year of Community Service

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                  Our universities are like our mothers. They take our grooming factor to heights. They build up our communication skills. They tell us how to present things in front of others. They make up our body languages and most of all they take our confidence to infinity by removing all hesitations. Our universities especially public sectors provide us international level degree at very low and affordable cost which help us avail great opportunities. They polish our skills and make us able to do something creative and extraordinary. Universities nourish and groom us for years and surely, they have right over any one year of our life as well. We get services and nourishment from our universities and government.                We are quite lucky we because we got such things in our lives but there are millions of children on roads in Pakistan. Those students aren't lucky enough to get care from our society or government. They don't get proper nourishment. They don'
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Verilog HDL Codes (Vivado)

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Gates

Module 


module gatesfinal(
    output out1,
    output out2,
    output out3,
    output out4,
    input in1,
    input in2
    );
     and a1(out1, in1, in2);
     or o1(out2, in1, in2);
     xor x1(out3, in1, in2);
     not n1(out4, in1);
endmodule

Test Bench


module gatesfinal_test;
reg in1, in2;
    wire out1, out2, out3, out4;
    gatesfinal g(out1, out2, out3, out4, in1, in2);
    initial 
    begin
    in1 = 1'b0;
    in2 = 1'b0;
    #10
    in1 = 1'b1;
    in2 = 1'b0;
    #10
    in1 = 1'b0;
    in2 = 1'b1;
    #10
    in1 = 1'b1;
    in2 = 1'b1;
    end
endmodule


Mux 4 by 1

Module


module Four_To_One_Mux(
    output out,
    input i0,
    input i1,
    input i2,
    input i3,
    input s1,
    input s0
    );
    wire s1n,s0n;
    wire y0,y1,y2,y3;
    not(s1n,s1);
    not(s0n,s0);
    and a0(y0,i0,s1n,s0n);
    and a1(y1,i1,s1n,s0);
    and a2(y2,i2,s1,s0n);
    and a3(y3,i3,s1,s0);
    or o1(out,y0,y1,y2,y3);
endmodule

Test Bench


module Test_Four_To_One_Mux;
reg I0,I1,I2,I3;
reg S1,S0;
wire OUTPUT;
Four_To_One_Mux mymux(OUTPUT,I0,I1,I2,I3,S1,S0);
initial
begin
I0=1;I1=0;I2=0;I3=1;
#1 $display ("I0=%b,I1=%b,I2=%b,I3=%b\n",I0,I1,I2,I3);
S1=0;S0=0;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S1,S0,OUTPUT);
S1=0;S0=1;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S1,S0,OUTPUT);
S1=1;S0=0;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S1,S0,OUTPUT);
S1=1;S0=1;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S1,S0,OUTPUT);
end
endmodule


MUX 8 by 1

Module


module Eight_To_One_Mux(
    output out,
    input i0,
    input i1,
    input i2,
    input i3,
    input i4,
    input i5,
    input i6,
    input i7,
    input s0,
    input s1,
    input s2
    );
        wire s1n,s0n,s2n;
        wire y0,y1,y2,y3,y4,y5,y6,y7;
        not(s1n,s1);
        not(s0n,s0);
        not(s2n,s2);
        and a0(y0,i0,s2n,s1n,s0n);
        and a1(y1,i1,s2n,s1n,s0);
        and a2(y2,i2,s2n,s1,s0n);
        and a3(y3,i3,s2n,s1,s0);
        and a4(y4,i4,s2,s1n,s0n);
        and a5(y5,i5,s2,s1n,s0);
        and a6(y6,i6,s2,s1,s0n);
        and a7(y7,i7,s2,s1,s0);
        or o1(out,y0,y1,y2,y3,y4,y5,y6,y7);
endmodule

Test Bench 


module Test_Eight_To_One_Mux;
reg I0,I1,I2,I3,I4,I5,I6,I7;
reg S1,S0,S2;
wire OUTPUT;
Eight_To_One_Mux mymux(OUTPUT,I0,I1,I2,I3,I4,I5,I6,I7,S1,S0,S2);
initial
begin
I0=1;I1=0;I2=1;I3=0;I4=1;I5=0;I6=1;I7=0;
#1 $display ("I0=%b,I1=%b,I2=%b,I3=%b\n",I0,I1,I2,I3,I4,I5,I6,I7);
S2=0;S1=0;S0=0;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S2,S1,S0,OUTPUT);
S2=0;S1=0;S0=1;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S2,S1,S0,OUTPUT);
S2=0;S1=1;S0=0;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S2,S1,S0,OUTPUT);
S2=0;S1=1;S0=1;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S2,S1,S0,OUTPUT);
S2=1;S1=0;S0=0;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S2,S1,S0,OUTPUT);
S2=1;S1=0;S0=1;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S2,S1,S0,OUTPUT);
S2=1;S1=1;S0=0;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S2,S1,S0,OUTPUT);
S2=1;S1=1;S0=1;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S2,S1,S0,OUTPUT);
end  
endmodule



ONE BIT FULL ADDER

Module

module OBFA(
    output sum,
    output c_out,
    input a,
    input b,
    input c_in
    );
    wire d,e,f;
    
    xor x1 (d,a,b);
    and a1 (e,a,b);
    
    xor x2 (sum,c_in,d);
    and a2 (f,d,c_in);
    
    or o1  (c_out,e,f);
endmodule

Test Bench

module Test_OBFA;
  reg a,b,c_in;
  wire sum,c_out;
  OBFA ob_fa(sum,c_out,a,b,c_in);
  //OBFA uut(.a(a),.b(b),.c_in(c_in),.sum(sum),.c_out(c_out));

  initial
  begin
  #10 a=1'b0; b=1'b0; c_in=1'b0;
  #10 a=1'b0; b=1'b0; c_in=1'b1;
  #10 a=1'b0; b=1'b1; c_in=1'b0;
  #10 a=1'b0; b=1'b1; c_in=1'b1;
  #10 a=1'b1; b=1'b0; c_in=1'b0;
  #10 a=1'b1; b=1'b0; c_in=1'b1;
  #10 a=1'b1; b=1'b1; c_in=1'b0;
  #10 a=1'b1; b=1'b1; c_in=1'b1;
  end   
endmodule



MUX 16 by 1 (Using 4 by 1)

Module

module Sixteen_By_One_Mux(
    output out,
    input in1,
    input in2,
    input in3,
    input in4,
    input in5,
    input in6,
    input in7,
    input in8,
    input in9,
    input in10,
    input in11,
    input in12,
    input in13,
    input in14,
    input in15,
    input in16,
    input s0,
    input s1
    );

            wire s1n,s0n;
            wire y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,y14,y15,y16,x1,x2,x3,x4,z1,z2,z3,z4;
            
            not(s1n,s1);
            not(s0n,s0);
            
            and a1(y1,in1,s1n,s0n);
            and a2(y2,in2,s1n,s0);
            and a3(y3,in3,s1,s0n);
            and a4(y4,in4,s1,s0);
            or o1(x1,y1,y2,y3,y4);
            
            and a5(y5,in5,s1n,s0n);
            and a6(y6,in6,s1n,s0);
            and a7(y7,in7,s1,s0n);
            and a8(y8,in8,s1,s0);
            or o2(x2,y5,y6,y7,y8);
            
            and a9(y9,in9,s1n,s0n);
            and a10(y10,in10,s1n,s0);
            and a11(y11,in11,s1,s0n);
            and a12(y12,in12,s1,s0);
            or o3(x3,y9,y10,y11,y12);
            
            and a13(y13,in13,s1n,s0n);
            and a14(y14,in14,s1n,s0);
            and a15(y15,in15,s1,s0n);
            and a16(y16,in16,s1,s0);
            or o4(x4,y13,y14,y15,y16);
            
            and f0(z1,x1,s1n,s0n);
            and f1(z2,x2,s1n,s0);
            and f2(z3,x3,s1,s0n);
            and f3(z4,x4,s1,s0);
            or o5(out,z1,z2,z3,z4);           
endmodule

Test Bench

module Test_Sixteen_By_One_Mux;

reg I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15,I16;
reg S1,S0;
wire OUTPUT;
Sixteen_By_One_Mux mymux(OUTPUT,I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15,I16,S1,S0);
initial
begin
I1=1;I2=0;I3=1;I4=0;
I5=0;I6=1;I7=0;I8=1;
I9=1;I10=0;I11=0;I12=1;
I13=0;I14=1;I15=1;I16=0;
#1 $display ("I0=%b,I1=%b,I2=%b,I3=%b\n",I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15,I16);
S1=0;S0=0;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S1,S0,OUTPUT);
S1=0;S0=1;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S1,S0,OUTPUT);
S1=1;S0=0;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S1,S0,OUTPUT);
S1=1;S0=1;
#1 $display ("S1=%b,S0=%b,OUTPUT=%b\n",S1,S0,OUTPUT);
end
endmodule



4 BIT ADDER (Using 1 bit Adder)

Module

    input sum3,
    input c_out,
    input a0,
    input a1,
    input a2,
    input a3,
    input b0,
    input b1,
    input b2,
    input b3,
    input c_in
    );
    
    wire c1, c2, c3;
         
         fulladder1bit F1(sum0,c1,a0,b0, c_in);
         fulladder1bit F2(sum1,c2,a1,b1,c1);
         fulladder1bit F3(sum2,c3,a2,b2,c2);
         fulladder1bit F4(sum3,c_out,a3,b3, c3);
          
    endmodule
    
    module fulladder1bit(
        output sum,
        output carry,
    
    input a,
    input b,
    input c
        );
        
        wire d,e,f;
        
        xor x1 (d,a,b);
        and a1 (e,a,b);
        
        xor x2 (sum,c,d);
        and a2 (f,d,c);
        
        or o1  (carry,e,f);
        
    endmodule

Test Bench

module Test_FBAUOBA;

reg a0;
reg b0;
reg a1;
reg b1;
reg a2;
reg b2;
reg a3;
reg b3;
reg c_in;
wire sum0;
wire sum1;
wire sum2;
wire sum3;
wire c_out;

FBAUOBA test(
.a0(a0), 
.b0(b0), 
.a1(a1), 
.b1(b1), 
.a2(a2), 
.b2(b2), 
.a3(a3), 
.b3(b3), 
.c_in(c_in), 
.sum0(sum0), 
.sum1(sum1), 
.sum2(sum2), 
.sum3(sum3), 
.c_out(c_out)
);

initial
begin
//1+2
a3 = 0; a2 = 0; a1 = 0; a0 = 1; 
b3 = 0; b2 = 0; b1 = 1; b0 = 0; 
c_in= 0;
#100
//3+4
a3 = 0; a2 = 0; a1 = 1; a0 = 1; 
b3 = 0; b2 = 1; b1 = 0; b0 = 0; 
c_in = 0;
#100
//4+5
a3 = 0; a2 = 1; a1 = 0; a0 = 0; 
b3 = 0; b2 = 1; b1 = 0; b0 = 1; 
c_in = 0;
#100
//5+6
a3 = 0; a2 = 1; a1 = 0; a0 = 1; 
b3 = 0; b2 = 1; b1 = 1; b0 = 0; 
c_in = 0;
#100
//6+7
a3 = 0; a2 = 1; a1 = 1; a0 = 0; 
b3 = 0; b2 = 1; b1 = 1; b0 = 1; 
c_in = 0;
#100
//7+8
a3 = 0; a2 = 1; a1 = 1; a0 = 1; 
b3 = 1; b2 = 0; b1 = 0; b0 = 0; 
c_in = 0;
#100;
end

    
endmodule


Decoder

Module

module Decoder(
    output out1,
    output out2,
    output out3,
    output out4,
    input in1,
    input in2
    );
    
    wire in1n,in2n;
    not(in1n,in1);
    not(in2n,in2);
    and a1(out1, in1n, in2n);
    and a2(out2, in1n, in2);
    and a3(out3, in1, in2n);
    and a4(out4, in1, in2);
endmodule

Test Bench

module Test_Decoder;

    reg in1, in2;
    wire out1, out2, out3, out4;
    Decoder d(out1, out2, out3, out4, in1, in2);
    initial 
    begin
    in1 = 1'b0;
    in2 = 1'b0;
    #10
    in1 = 1'b1;
    in2 = 1'b0;
    #10
    in1 = 1'b0;
    in2 = 1'b1;
    #10
    in1 = 1'b1;
    in2 = 1'b1;
    end
    
endmodule




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Comments

  1. UnknownOctober 16, 2018 at 7:28 PM

    Thanks for sharing your knowledge. Keep doing good work.

    ReplyDelete
  2. EurtugrulOctober 16, 2018 at 9:16 PM

    Gud work sitg!
    Aap hm sb ka bhala krtay hain allah aap ka vhala kray😁

    ReplyDelete
  3. UnknownOctober 17, 2018 at 12:41 AM

    Good Work

    ReplyDelete

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