Posts

Showing posts with the label DataFlow

Should All Pakistani Students Studying in Universities Complete A Year of Community Service

-
Image
                  Our universities are like our mothers. They take our grooming factor to heights. They build up our communication skills. They tell us how to present things in front of others. They make up our body languages and most of all they take our confidence to infinity by removing all hesitations. Our universities especially public sectors provide us international level degree at very low and affordable cost which help us avail great opportunities. They polish our skills and make us able to do something creative and extraordinary. Universities nourish and groom us for years and surely, they have right over any one year of our life as well. We get services and nourishment from our universities and government.                We are quite lucky we because we got such things in our lives but there are millions of children on roads in Pakistan. Those students aren't lucky enough to get care from...
1 comment
Read more

Verilog HDL using Data Flow

-
Image
Verilog codes using Data Flow Create 4x1 Mux using Data Flow Module module Four_by_One(     output out,     input i0,     input i1,     input i2,     input i3,     input s0,     input s1     );       assign out = (s1)?(s0?i3:i2):(s0?i1:i0); endmodule Test Bench module Test_Four_by_One; reg I0,I1,I2,I3; reg S1,S0; wire OUT; Four_by_One mymux(OUT,I0,I1,I2,I3,S1,S0); initial begin I0=1;I1=0;I2=0;I3=1; #10  S1=0;S0=0; #10  S1=0;S0=1; #10  S1=1;S0=0; #10  S1=1;S0=1; end endmodule Create 16x1 using Data Flow using 4x1 Module module Sixteen_by_One(     output out,     input i0,     input i1,     input i2,     input i3,     input i4,     input i5,     input i6,     input i7, ...
Post a Comment
Read more